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mc145074 1 motorola product preview

cmos the mc145074 is a high precision, stereo audio digitaltoanalog converter that utilizes second order sigmadelta modulators with 2tap fir feedback architecture. the part can be used as a stand alone stereo digital modulator, or as a companion part to the mc145076 smoothing filter to achieve high quality, low cost audio performance. ? peak s/(n+d) > 100 db ? single 5 v supply operation ? accepts 16, 18, or 20bit data words ? dual/single pin data input modes ? programmable wclk divider ? operating temperature range: 40 to + 85 c ? low power consumption: 40 mw typical ? companion to mc145076 stereo audio fir smoothing filter 2 stby dil/wdly dir/dilr bclk dmode res1 res0 3 4 5 13 14 15 control logic serial/parallel interface offset scaler s d modulator chop dol dor 16 serial/parallel interface offset scaler s d modulator chop 9 6 wclk timing mstr div2 7 x out x in 12 11 8 1 v dd v ss left channel right channel 10 this document contains information on a product under development. motorola reserves the right to change or discontinue this product without notice. order this document by mc145074/d semiconductor technical data pin assignment d suffix 16 pin soic case 751b05 ordering information MC145074D soic package 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 x in dmode res1 res0 dol dor div2 x out dir/dilr dil/wdly stby v ss mstr wclk bclk v dd 16 1 ? motorola, inc. 1996 rev 1 5/96
mc145074 motorola 2 maximum ratings* (voltages referenced to v ss ) symbol parameter value unit v dd dc supply voltage 6.0 v v in dc input voltage, any digital input v ss 0.5 to v dd + 0.5 v i in dc input current, per pin 10 ma t stg storage temperature 55 to 150 c t l lead temperature, 1 mm from case for 10 seconds 260 c * maximum ratings are those values beyond which damage to the device may occur. func- tional operation should be restricted to the operation ranges below. operation ranges (applicable to guaranteed limits) symbol parameter value unit v dd dc supply voltage, referenced to v ss 4.5 to 5.5 v v in , v out digital input/output voltage v ss 0.5 to v dd + 0.5 v i d input pin current drain 1 m a t a operating temperature 40 to + 85 c dc electrical characteristics (voltages referenced to v ss , full temperature and voltage ranges per operation ranges table, unless otherwise indicated) symbol parameter min typ max unit i dd power supply current e e 10 ma v il v ih input voltage low level input high level input e v dd x 0.7 e e v dd x 0.3 e v v ol v oh output voltage low level output (load = 0.4 ma) high level output (load = 0.4 ma) e v dd 0.3 e e 0.3 e v i lkg input leakage current e e 10 m a this device contains protection circuitry to guard against damage due to high static volt- ages or electric fields. however, precautions must be taken to avoid applications of any volt- age higher than maximum rated voltages to this highimpedance circuit. for proper opera- tion, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open.
mc145074 3 motorola ac electrical characteristics (full temperature and voltage ranges per operation ranges table at 50 pf loads on outputs) symbol parameter figure guaranteed limit unit operating frequency x in (div2 = 0) (div2 = 1) 18.5 37.0 mhz bit clock frequency 18.5 mhz t r , t f maximum rise and fall times (bckl, wclk) 2, 5 6 ns t plh t tlh x out lh propagation delay x out rise time 2 30 15 ns t phl t thl x out hl propagation delay x out fall time 2 30 15 ns t plh t tlh dol, dor lh propagation delays dol, dor rise time 3 15 5 ns t phl t thl dol, dor hl propagation delays dol, dor fall time 3 15 5 ns t plh t tlh wclk output lh propagation delay wclk output rise time 4 15 5 ns t phl t thl wclk output hl propagation delay wclk output fall time 4 15 5 ns t su t h dir master program mode minimum setup time dir master program mode minimum hold time 5 5 5 ns t su t h dir, dil minimum setup time dir, dil minimum hold time 5 5 5 ns t su t h wclk minimum setup time to bclk (not dmode = wdly = 1) wclk minimum hold time to bclk (not dmode = wdly = 1) 6 5 5 ns t su t h wclk minimum setup time to x in (not dmode = wdly = 1) wclk minimum hold time to x in (not dmode = wdly = 1) 6 5 5 ns t su t h wclk minimum setup time to bclk (dmode = wdly = 1) wclk minimum hold time to bclk (dmode = wdly = 1) 7 5 5 ns t lag t lead bclk to x in (1st edge only) lag time (dmode = wdly = 1) bclk to x in (1st edge only) lead time (dmode = wdly = 1) 7 5 5 ns
mc145074 motorola 4 switching waveforms 10% x in 90% 50% t r t phl 90% 50% 10% t f 10% 90% 50% 90% 50% 10% t plh t thl t tlh x out figure 1. x out propagation delay timing 50% 10% 90% 50% 90% 50% 10% t thl t tlh 50% x in dol/dor t phl t plh figure 2. dol/dor propagation delay timing x in 50% t phl 10% 90% 50% 90% 50% 10% t plh t thl t tlh wclk 50% figure 3. wclk out propagation delay timing (master mode) 10% 90% bclk dil/dir/dilr t f 50% 90% 50% t r 10% t h t r t f t su t su figure 4. dil/dir/dilr setup and hold timing bclk wclk 50% 50% 50% t h t su t su t h x in figure 5. wclk timing (all modes except dmode = 1, wdly = 1) x in wclk 50% 50% 50% t lag t lead t su t h bclk figure 6. wclk timing (dmode = 1, wdly = 1) bits 16 18 20 osr s/(n+d) db s/(n+d) db s/(n+d) db 128x 90 90 90 192x 94 98 99 256x 95 103 105 384x 96 107 113 note: values are for 0 db input signal, 0 20 khz bw, and 44.1 khz 1x fs sampling rate. figure 7. digital s/(n+d) performance levels
mc145074 5 motorola pin descriptions v dd positive device supply (pin 1) v dd is the positive supply, nominally + 5 volts. stby activelow standby input (pin 2) a low level on the stby pin will force the device into a standby state. if the device is being operated in the master mode (mstr = 1), the wclk internal divider can be programmed using the dir/dilr, and bclk pins while the stby pin is active. when the device is in standby, the dol and dor pins will output a 50% duty cycle data stream that will generate a 1/2 scale analog output, when averaged through the output filter. dil/wdly left channel data/word clock delay input (pin 3) when the dmode pin is low, this pin is the left channel (msb first) 2's complement serial data input. when the dmode pin is high, this pin controls the wclk delay. a high level on this pin will delay the wclk an additional clock cycle internal to the device. dir/dilr right channel data/multiplexed left right data input (pin 4) when the dmode pin is low, this pin is the right channel (msb first) 2's complement serial data input. when the dmode pin is high, this pin is the multiplexed left then right channel data input. if the part is being operated in the master mode (mstr = 1), the wclk internal divider can be pro- grammed by clocking control word data onto this pin with the bclk pin while the device is in the standby mode (stby = 0). bclk bit clock input (pin 5) the bclk pin provides the serial bit shift clock for the left and right channel data in all modes of operation. a rising edge on the bclk pin shifts serial data into the device. wclk word clock output/input (pin 6) the wclk pin is used to latch the shifted serial data word into the device. the mc145074 can accept an external word clock when in the slave mode, or can use an internally generated word clock when operating in the master mode. when dmode is low, left and right channel data is latched into the device on the falling edge of wclk . when dmode is high, left channel data is latched on the rising edge of wclk and right channel data is latched on the falling edge of wclk with both channel inputs being input to the modulator on the next rising edge of wclk . the internal divide ratio used to generate wclk , as well as the rising or falling edge latching of the input data can be programmed using the dir/ dilr and bclk pins while the device is in the standby mode. mstr activehigh master mode select input (pin 7) a high level on the mstr pin will select the master mode of operation. in the master mode, the mc145074 will generate and output a word clock signal on the wclk pin. a low level on the mstr pin will place the mc145074 in the slave mode, and the wclk signal must be provided by an external source. the default master mode divide rate is modclk/64. v ss device ground (pin 8) v ss is normally connected to ground. dor right channel data output (pin 9) dor is the right channel modulator data output. div2 master clock divide control input (pin 10) div2 is the x in divide by two control pin. when cleared, the x in pin directly provides the modulator clock (modclk), and the data output bit streams are not chopped. when this pin is set, the x in clock is divided by two to provide the modulator clock and the output data bit stream is chopped at the x in fre- quency using an alternating 1,0 chop. the chop is used to reduce even order distortion for a standalone application without the mc145076. the reconstructed output signal will drop 6db due to the chopping. x out master clock output (pin 11) x out is the inverted output signal of x in and may be used for a buffered clock output or for a crystal oscillator. x in master clock input (pin 12) x in is the input clock pin for the mc145074, and may be used with x out as the inverter for a crystal oscillator. dmode data mode input (pin 13) a low level on the dmode pin will select the dual data pin mode of operation. in this mode, the serial input data is entered on the dir and dil pins. a high level on the dmode pin selects the multiplexed mode of operation. in this mode, the left and right channel serial input data must be multi- plexed on the dir/dilr pin. res0 and res1 input data resolution pins (pins 14, 15) the res0 and res1 pins select the length of the serial data word input to the mc145074. the serial input data can be 16, 18, or 20bits in length with the most significant bits clocked in first. figure 9 lists the serial interface formats. dol left channel data output (pin 16) dol is the left channel modulator data output.
mc145074 motorola 6 dmode res1 res0 operating mode 0 0 0 dual data pin 16bit input 0 0 1 dual data pin 18bit input 0 1 0 dual data pin 20bit input 0 1 1 factory test mode 1 0 0 single data pin 16bit input 1 0 1 single data pin 18bit input 1 1 0 single data pin 20bit input 1 1 1 factory test mode figure 8. serial interface formats functional description the mc145074 is a high precision stereo audio digital toanalog converter, which utilizes a secondorder sigma delta modulator with a patented 2tap architecture that significantly reduces problems normally associated with onebit sigmadelta technology. normally, a second order modulator can develop patterns in the digital output repre- sentation of small signals and with small dc input offsets. it is common to add dither to mask these effects, but a reduc- tion of dynamic range can result. the implementation used in the mc145074 has considerable immunity to these trouble- some inputs, and without performance compromise. with rc filtering, the mc145074 can be used as a stand alone stereo digital modulator for applications with modest requirements. high performance can be realized with the companion mc145076 stereo audio fir smoothing filter, which reduces the inband im products formed by large am- plitude spectral components of the outofband noise shap- ing, clock corruption, and power supply noise. the mc145074 has been designed for maximum flexibility and is well suited for high fidelity audio and multimedia applications. if used in conjunction with a differential mc145076 smoothing filter, a peak s/(n+d) ratio of > 100 db can be achieved by utilizing 18 or 20bit input data and a 256x oversampling ratio. the mc145074 has a maximum operating frequency of 18.5 mhz, and can be used with any sampling rate including 32, 44.1, or 48 khz. the mc145074 can accept a 1x, or a 2x input clock with serial data output chop. the device can accept 16, 18, or 20bit digital data in a dual data pin input format, or single pin multiplexed format. an offset scaler is included to allow 0 db digital inputs while maintaining low distortion. the offset, scaled data is applied to the d/a modulator before being op- tionally chopped (2x mode), and sent to an external smooth- ing filter. when this device is used with the mc145076, dividing the clock down or using the chop mode is not neces- sary. timing circuit the internal timing circuits of the mc145074 are driven by the x in clock. when the div2 pin is active high, the mc145074 divides the x in clock by two to generate the in- ternal modulator clock (modclk), and uses the x in clock frequency to chop the output data using a 50% chop signal. when the mc145074 is operated in the master mode, the wclk pin is configured as an output. the wclk output is generated by dividing down the modulator clock. the divide ratio of the internal frequency divider can be programmed utilizing a 5bit control word while the mc145074 is in the standby mode. the 5bit control word is defined as the last 5bits (msb first) that are clocked into the dir/dilr pin using the bclk signal. when cleared, the most significant bit of the control word indicates that the wclk signal is nega- tive edge triggered (just as in the slave mode). if the most significant bit is set, the wclk is positive edge triggered. the next three most significant or middle three bits of the control word determine the value of the divide ratio of the in- ternal frequency divider. the least significant bit of the 5bit control word indicates a prescaler divide by two when cleared, and divide by three when set. the divider modes are summarized in figure 10. note the default mode of operation is control word $06 which provides a wclk signal (negative edge triggered) at a frequency of 1/64 the modu- lator clock frequency. this is the preferred operat- ing mode of 256x osr and 4x fir. control word value (hex) divide ratio wclk edge control word value (hex) divide ratio wclk edge 0 8 10 8 1 12 11 12 2 16 12 16 3 24 13 24 4 32 14 32 5 48 15 48 6 64 16 64 7 96 17 96 8 128 18 128 9 192 19 192 a 256 1a 256 b 384 1b 384 c 512 1c 512 d 768 1d 768 e 1024 1e 1024 f 1536 1f 1536 figure 9. wclk divider modes offset scaler second order sigmadelta modulators typically give up about 2 db of dynamic range and an adjustment to the digital input words must be made if full scale digital input word recognition is desired. the offset scaler circuitry of the mc145074 digitally attenuates the input linearly to 3/4 or approximately 2.5 db. figure 11 illustrates the function of the offset scaler block. an ideal dac would perform as shown in curve one, but the sigmadelta modulator actually operates as shown in curve two. the digital input words to the mc145074 are attenuated to 3/4. this allows the mc145074 to operate on all 2's compliment digital inputs from $80000 to $7ffff, with the resulting response shown in curve three. in addition to scaling the digital input word, the offset scaler adds a digital dc offset of 1/8th to recenter the digital input word so that the mc145074 output signal is cen- tered around v dd /2.
mc145074 7 motorola $80000 $7ffff 1 20bit digital input scaler output scaler transfer function 3/4 scale = 2.5 db 1 ideal 2 actual 3 compensated 3 2 figure 10. offset scaler operation serial interface and control logic the serial interface and control logic of the mc145074 may be configured to accept 16, 18, or 20bit data words by applying the appropriate logic levels to the res1 and res0 pins. the dmode input pin configures the serial interface to accept 2's complement data (msb first) in a dual data pin or single pin, multiplexed input format. it should be noted that in some cases when using the single data pin input mode and a large osr, the bclk rate may be too high for some dsps, unless an interface circuit is added. figure 9 shows the avail- able serial interface formats of the mc145074. when operating in a dual data pin mode, 2's complement data words are serially input from the dir and dil pins as shown in figure 12. a rising edge on bclk serially shifts in the data present on the dir and dil inputs. after all data bits of an input word are shifted in, a falling edge on wclk latches the data word into the mc145074. the bclk can be a continuous clock as long as the serial input data word is right justified in the word time, or as long as there exists one and only one bclk cycle for every data bit input to the device. when operating in a single pin multiplexed mode, the dir input pin is reconfigured as the dilr pin. left and right chan- nel serial input data is multiplexed into the mc145074 on the dilr pin, and is serially shifted into the part using bclk as shown in figure 13. when wdly is low, left channel data is latched into the part on the rising edge of wclk , and right channel data is latched on the falling edge of wclk . as in the dual data pin mode, the bclk can be either an asynchro- nous or continuous clock as long as the serial input data word is right justified in the word time. forcing wdly high al- lows the wclk cycle to appear one clock cycle early as shown in figure 14.
mc145074 motorola 8 figure 11. dmode = 0 serial interface timing diagram wclk bclk dir dil 191817161514131211109876543210 191817161514131211109876543210 19 18 17 16 15 14 19 18 17 16 15 14 dmode = 0, 16/18/20-bits in : 10 10 x x x x
mc145074 9 motorola figure 12. dmode = 1, wdly = 0, serial interface timing diagram bclk dilr 191817161514131211109876543210 191817161514131211109876543210 191817161514131211109876543210 (left channel) n (right channel) n (left channel) n + 1 dmode = 1, wdly = 0, 384x clock, 16/18/20 bits in: dmode = 1, wdly = 0, 8x input, 256x clock, 16 bits in: (left channel) n (right channel) n (left channel) n + 1 15141312111098765432101514131211109876543210151413121110987654 3210 wclk bclk dilr wclk x x x x
mc145074 motorola 10 figure 13. dmode = 1, wdly = 1, serial interface timing diagram 191817161514131211109876543210 191817161514131211109876543210 191817161514131211109876543210 (left channel) n (right channel) n (left channel) n + 1 dmode = 1, wdly = 1, 384x clock, 16/18/20 bits in: dmode = 1, wdly = 1, 8x input, 256x clock, 16 bits in: (left channel) n (right channel) n (left channel) n + 1 15141312111098765432101514131211109876543210151413121110987654 3210 bclk dilr wclk bclk dilr wclk x x x x
mc145074 11 motorola stby dil dir bclk wclk + 5 v 10 f 4640 22 pf 22 pf 200 200 k 16.9344 mhz 1000 2000 1000 1000 mc33077 m 10 f m + 499 499 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 1000 1000 0.01 f m w + + 0.1 f m + figure 14. low cost + 5 v stereo audio system, typically 88 db s/(n+d) v l v r + 5 v + 5 v * all resistors 1% + 5 v mc145076 mc145074
mc145074 motorola 12 stby dil dir bclk wclk 22.5792 mhz 249 249 16 15 14 13 12 11 10 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 1000 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 249 249 1000 1000 1000 1000 1000 + 5 v 0.01 f m 1/6 mc74hc04 10 f m + 10 f m + 1/6 mc74hc04 10 f m + 0.1 m f + + 1000 200 k w figure 15. mid performance stereo audio system, typically 98 db s/(n+d) mc145074 mc145076 4640 4640 22 pf 22 pf + 5 v + 5 v 5 v 5 v v r * all resistors 1% + 5 v v l mc33077 mc145076
mc145074 13 motorola stby dil dir bclk wclk 22.5792 mhz 1000 2000 1000 1000 499 499 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 1000 1000 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 499 499 1000 1000 1000 1000 1000 1000 1000 1000 1000 + 5 v 0.01 f m 1/6 mc74hc04 10 f m + 10 f m + 1/6 mc74hc04 10 f m + 0.1 m f + + + + + + 1000 200 k w figure 16. high performance stereo audio system, typically 105 db s/(n+d) mc145074 mc145076 mc145076 4640 4640 22 pf 22 pf + 5 v + 5 v + 5 v + 5 v + 5 v + 5 v 5 v 5 v v l v r * all resistors 1% mc33077 + 5 v
mc145074 motorola 14 soic package case 751b05 0.25 (0.010) t b a m s s min min max max millimeters inches dim a b c d f g j k m p r 9.80 3.80 1.35 0.35 0.40 0.19 0.10 0 5.80 0.25 10.00 4.00 1.75 0.49 1.25 0.25 0.25 7 6.20 0.50 0.386 0.150 0.054 0.014 0.016 0.008 0.004 0 0.229 0.010 0.393 0.157 0.068 0.019 0.049 0.009 0.009 7 0.244 0.019 1.27 bsc 0.050 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 1 8 9 16 -a- -b- d 16 pl k c g -t- seating plane r x 45 m j f p 8 pl 0.25 (0.010) b m m package dimensions motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, 6f seibubutsuryucenter, p.o. box 20912; phoenix, arizona 85036. 18004412447 or 6023035454 3142 tatsumi kotoku, tokyo 135, japan. 038135218315 mfax : rmfax0@email.sps.mot.com touchtone 6 022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, internet : http://designnet.com 51 ting kok r oad, tai po, n.t., hong kong. 85226629298 mc145074/d
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